Cooperative register assignment and code compaction for digital signal processors with irregular datapaths
نویسندگان
چکیده
We address the phase ordering problem of code compaction and register assignment in a data ow graph compiler. During register assignment, we take into account the instructionlevel parallelism available. Symbolic variables in straightline code are allocated to register set/memory location pairs which maximally preserve the freedom available for code compaction. Whenever necessary, spill code is inserted during nal register assignment and scheduled during code compaction. Register assignment is performed taking into account its impact on code compaction. This strategy results in nal code of high quality.
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